Alif Semiconductor /AE302F80F55D5AE_CM55_HE_View /LPSPI /SPI_DMARDLR

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Interpret as SPI_DMARDLR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DMARDL

Description

DMA Receive Data Level Register

Fields

DMARDL

Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level is equal to DMARDL + 1; that is, receive DMA request is generated when the number of valid data entries in the receive FIFO is equal to or above this bit field value + 1, and SPI_DMACR[RDMAE] = 0x1.

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